The present invention generally relates to fabrication of semiconductor devices and more particularly to a testing of a semiconductor device during a fabrication process of the same and a test data processor used in such testing for creating test data.
With increase in the integration density, the magnitude of integrated circuits is increasing ever and ever. In such very large-scale integrated circuits, the testing for verifying proper operation of the integrated circuit becomes an important problem.
Conventionally, testing of integrated circuits has been made by using simulation data, which represents the expected functional operation of an integrated circuit produced by software simulation, wherein the simulation data is generally provided in the form of sampling data sampled in a time axis with a predetermined sampling interval. The simulation data thus sampled is then processed by a test data processor that converts the sampled simulation data thus obtained into test data suitable for use in actual testing of the integrated circuit. It should be noted that the testing of the integrated circuit is conducted by a tester device while using the test data which represents the result of the simulation in terms of operational cycles. Typically, the test data is produced by sampling the simulation data with a specific sampling interval having a period coincident with the interval of the operational cycle.
FIG. 1 and FIGS. 2A-2D represent a conventional example conducted by a test data processor for converting simulation data into test data, wherein FIG. 1 represents the flowchart of the test data processor while FIGS. 2A-2D represent examples of event information and cycle information of the test data. It should be noted that the event information represents the timing of the simulation data, while the cycle information represents the event information for each cycle thus obtained by sampling the simulation data with the predetermined sampling interval.
Hereinafter, the process of verifying the operation of an integrated circuit 100 of FIG. 2A will be described with reference to the flowchart of FIG. 1. In the example of FIG. 2A, the integrated circuit 100 has input terminals 101 and 102 and an output terminal 103.
Referring to FIG. 1, a step S100 is conducted first, in which the event (transition of state) is detected for the signals appearing on the input/output terminals 101-103 from the diagram of FIG. 2B, wherein FIG. 2B represents the state of the signals appearing at the input/output terminals 101-103. It should be noted that the diagram of FIG. 2B is obtained as a result of the software simulation on the function of the integrated circuit 100 and indicates that the integrated circuit 100 produces an output signal on the output terminal 103 in response to input signals supplied to the input terminals 101 and 102.
After the step S100, a step S110 is conducted on the simulation data of FIG. 2B to extract therefrom test timing information represented in FIG. 2D. It should be noted that the test timing information of FIG. 2D is necessary when sampling the event information included in the simulation data of FIG. 2B to produce the test data.
Referring to FIG. 2D, the test timing information includes: a timing number TNO used to discriminate a plurality of different test timing information from each other; cycle information CYCLE indicative of the sampling interval used for sampling the event information from the simulation data of FIG. 2B; and an event discriminator that represents the mode of signal transition for each of the signals appearing on the input terminals 101 and 102 and the output terminal 103, wherein it should be noted that the event discriminator is used to discriminate the signal transition mode occurring in each sampling interval. For example, a representation such as NRZ or RZ may be used for the event discriminator, wherein NRZ represents the non-return-to-zero transition mode while RZ represents the return-to-zero transition mode. In the illustrated example, there is only one TNO, while there can be a number of different timing numbers TNO corresponding to different test timing information, wherein such different test timing information are used as a template for sampling the simulation data of FIG. 2B with respective, mutually different timings and sampling intervals or cycles.
After the step S110, the process proceeds to a step S120 wherein the simulation data of FIG. 2B is sampled according to the test timing information of FIG. 2D for each TNO, and a step S130 is conducted subsequently wherein test data represented in FIG. 2C is produced in the step S130 from the simulation data sampled in the step S120. It should be noted that the test data contains therein, in addition to the timing number TNO, the logic state of the signals of the input and output terminals 101-103 at the foregoing sampling timing specified by the TNO.
In the illustrated example of FIG. 2B, it should be noted that there exists only one event timing occurring every 5 ns (nanoseconds), and thus, there is only one timing information (TNO=xe2x80x9c1xe2x80x9d) as represented in FIG. 2D. As noted before, however, there can be a number of additional event timings corresponding to TNO of other than xe2x80x9c1.xe2x80x9d
The test data of FIG. 2C thus formed has been used by a tester device for the testing of the integrated circuit 100.
However, the foregoing processing to form the test data by a sampling of the simulation data with a predetermined sampling interval or cycle has a drawback in that it is necessary to provide a number of different test timing information, such as the one represented in FIG. 2D with the TNO of xe2x80x9c1,xe2x80x9d in correspondence to the event information of the simulation data to be processed. It should be noted that such test timing information is used as a prior template when extracting the test data such as the one represented in FIG. 2C from the simulation data of FIG. 2B. However, such a process of preparing different templates is complex and takes a substantial time. Thereby, the efficiency of fabrication of the integrated circuits, which includes such a testing process, is inevitably deteriorated.
Further, such a conventional testing process has required that the test data be formed based on exact test timing information in order to ensure that the sampling is made with proper timing. Otherwise, there may be oversight of events or offset in the timing of the events, and the processing of the test data back to the original simulation date may not be possible.
Further, the test data thus formed from the simulation data by sampling the simulation data tends to raise the problem of discrepancy in the accuracy between the simulation data and the tester device, as there is no adaptation made about the accuracy of between the simulation data and the testing conducted by the tester device. Thus, the test data may be unnecessarily accurate as compared with the test actually conducted by the tester device. Alternatively, there may be a case in which the accuracy of the test data may be too rough for the testing by the tester device. In the latter case, no satisfactory testing of the integrated circuit is possible.
Further, because of the lack of ability of verification of semiconductor operation in the case of uncertain events such as incoming of noise, the foregoing conventional process of forming the test data has a problem in that the verification of such uncertain events, which may require accuracy exceeding the accuracy of measurement of the tester device, is not possible.
Further, the conventional process of forming the test data suffers from the problem, when the cycle time used for testing the semiconductor device is too short, in that sufficient input/output dead band is not secured. It should be noted that such an input/output dead band is necessary for switching the state of the semiconductor device between an input state and an output state. Thereby, the testing of the semiconductor device is not possible with the desired precision.
Accordingly, it is a general object of the present invention to provide a novel and useful method of forming test data for testing a semiconductor device and a fabrication process of a semiconductor device including a testing process using such test data, wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a method of creating test data used for testing a semiconductor device, from simulation data simulating a function of said semiconductor device, comprising the steps of:
detecting a transition of state of said simulation data; and
creating said test data in response to said detected transition of said simulation data.
According to the present invention, the process of preparing sampling information as template is eliminated, and the simulation data is converted directly to the test data. Thereby, the process of provide a number of different templates in advance is eliminated also, and the creation of the test data is conducted easily and efficiently. As the test data is formed based on the actual transition of state of the simulation data, there is no chance that the test data misses the transition in the simulation data, and the testing of the semiconductor device is conducted with reliability and accuracy.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.